Wednesday, January 30, 2008

Intel likely to reveal details of Silverthorne next week

Intel will offer a detailed look at a new processor next week during a presentation at the International Solid State Circuits Conference (ISSCC) that should set the stage for an unexpectedly close battle with Taiwan's Via Technologies.
Intel's presentation will cover technical details of an unnamed low-power processor that is made using a 45-nanometer process and designed for mobile Internet devices, according to an abstract contained in the ISSCC program. That's the same general description used by Intel to describe its upcoming Silverthorne processor.

Intel executives declined to confirm whether the ISSCC presentation covers Silverthorne but said the abstract provided an accurate description of the unspecified processor. If the chip described is indeed Silverthorne, the presentation appears set to confirm many rumored details of the chip's architecture and characteristics.

Most importantly, Silverthorne is rumored to be an in-order processor, the same as the processor Intel will detail next week, according to the abstract.

In layman's terms, this means the chip functions like a factory with a single assembly line and is capable of processing one operation at a time. An in-order processor must complete that operation before it can move on to another operation. This is a different chip architecture from that used in Intel's other processors but it's the same as Via Technologies' low-power C7 chip, which has proved popular among the portable device makers that are Silverthorne's target market.

The processor that Intel will discuss next week is also a dual-issue processor, just as Silverthorne is rumored to be. This feature -- which Intel is likely to emphasize at ISSCC -- allows two instructions to be issued at a time and should give Silverthorne a performance advantage over the C7, which can issue only one instruction at a time.

If these rumored characteristics of Silverthorne are confirmed next week, the stage will be set for an unexpectedly close contest between Intel and Via's upcoming low-power Isaiah processors, which are also designed for small, portable computers.

Tiny by comparison to Intel and Advanced Micro Devices, Via has nevertheless managed to carve out a comfortable niche selling the inexpensive, low-power C7. Beset by a dying third-party chipset business, Via hopes to become a mainstream processor supplier with its upcoming Isaiah processors, which the company unveiled last week.

Unlike the C7 and Silverthorne, Isaiah uses a superscalar, out-of-order processor architecture. This architecture, which is used in high-end chips from Intel and AMD, generally offers better performance than an in-order design and is akin to a factory equipped with multiple assembly lines capable of processing different operations at the same time.

The performance of Isaiah is further enhanced by being superscalar, or having the ability to process multiple instructions during every clock cycle.

Centaur, the Via subsidiary that handles processor design for the company, is confident that Isaiah will outperform Silverthorne, even though an accurate comparison of both chips won't be possible until the two processors can be benchmarked and assessed by independent observers.

Nevertheless, Isaiah looks good on paper. Via chips based on the new architecture will offer 1M byte of L2 cache and support a front-side bus running at speeds up to 1.3GHz. By comparison, the chip that Intel will reveal next week has 512K bytes of cache and a 533MHz front-side bus.

But the ISSCC abstract raises as many questions as it appears to answer. For example, it doesn't specify how many cores the new Intel chip will use and gives no indication for how fast these cores will run.

Silverthorne, and a related processor called Diamondville, are widely expected to be available in single-core and dual-core versions. They are also expected to run at roughly the same clock speeds as the Isaiah chips, will be available in versions running from 400MHz up to 2GHz.

No comments: